The PDTrace™ architecture refers to a set of digital system debugging methodology and its implementations available through MIPS Technologies™, Inc., Mountain View, Calif. The PDTrace™ technology is described in U.S. Pat. Nos. 7,231,551; 7,178,133; 7,055,0707 and 7,043,668, the contents of which are incorporated herein by reference.
Current PDTrace™ technology supports single processor systems. It would be desirable to extend PDTrace™ technology to support multi-processor systems.
Time stamps or other high overhead techniques may be used to organize trace information from multiple processors. However, this results in voluminous information and large computational demands. Similarly, tracing information in a multi-processor system may result in information overload and long processing times.
Therefore, it is desirable to condense the amount of information to be processed, while still providing adequate information to support meaningful debugging operations. Ideally, different trace formats would be provided depending upon debugging requirements. In addition, an efficient technique to correlate information from different trace streams is desirable to reduce information bandwidth and processing times.